New Microchip Technology and The Death of Memory Explained

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Published 2024-07-12
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Modern CPUs, GPUs and SoCs have a major problem. SRAM memory scaling is dead. In this video I discuss new disruptive memory technology that may solve this problem.

Timestamps:
00:00 - Major Problem with Modern Chips
09:00 - Possible Solution
11:24 - New Memory Technology Explained

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All Comments (21)
  • Science communicators who actually are professionals in their field are allways welcome. Thank you Anastasi
  • @AdvantestInc
    You really have a knack for making complex topics engaging and easy to follow for everyone! Breaking down the challenges of SRAM and introducing phase change memory in such a clear manner is no small feat. Excited for more content like this!
  • @vicaya
    It's quite bizarre that you thought the PCM memory is a future replacement of SRAM, as the it has a switching speed of 40ns (on par with DRAM), according to the paper you cited. This is an order of magnitude slower than SRAM. The current only viable option to replace SRAM is SOT-MRAM, which TSMC is working on. Go research SOT-MRAM😁
  • When I first started programming, and RAM was off chip and typically a few KB, we'd spend a lot of dev time working out how to do as much as possible in as little RAM as possible and as few clock cycles as possible. These days the demands to cut development time and get new features out, more driven by senior management and Product Owners than by real customer demand, seems to have ditched those ideas. If it's too slow the customer is expected to just buy a higher spec machine and new developers are taught ways to shorten development time but not execution time. I think that this is a false economy. About 10 years ago I was able to shorten a big data-processing job from 3 days to under 20 minutes, on the same hardware, by applying the techniques I'd learned back in the 1980s to key functions. It took me 5 days, but when this is something that has to be run every week the saving soon stacks up
  • @IragmanI
    I'd be curious about the thermodynamic side effects of phase change memory during transitions as the crystallisation would release heat while amorphization would be cooling
  • @tappyuser
    Been waiting for your vid.... Love the content
  • @rchin75
    Thanks. Amazing video. It's kind of interesting how it always comes down to the same principles. First shrinking the size in 2D, then layering stuff, and eventually going into the 3rd dimension. And when that reaches its limits, then change the packaging and invent some hybrid setup. Next, change the materials and go nano or use light etc. instead. Even the success criteria are usually similar: energy consumption, speed or latency, size and area, cost of production, reliability and defect rate, and the integration with the existing ecosystem.
  • @bobclarke5913
    You explain things so well, thanks for a well thought out presentation
  • Very interesting. Thanks for sharing your expertise. There is always something interesting in your videos. At least in the three or four i have seen so far.😊
  • @timothym.3880
    So, the two biggest old school technologies that are slowing progress seems to be memory and batteries.
  • @garycard1826
    Very comprehensive and interesting video. Thanks Anastasi! 👍
  • That was a great video very informative. You're right, it is an exciting time to be alive with all the evolving technology.
  • This helps me immensely with my DD into the tech & companies involved in the memory sector, Thank you very much Anastasi!
  • The problem with chiplet design is heat management. Since every layer is active, it burns energy and produces heat, and this isn't good. A secondary problem is the bus interconnect because stacking requires shared lanes, so memory layers are in parallel, making the bus interconnect a bottleneck. Last but not least is signal strength and propagation time: stacking layers requires precise alignment and add electron jumping around, so there's a potential limiting factor in electron propagation, noise and eventual errors. This isn't much of a problem if the system is built around it, but it still is a limiting factor. There are solutions: since there's one master and multiple slaves there's no risk of collisions and so you can make a lot of assumptions on the drawing board... but busses are going to become wider and more complex, and that will add latency where you don't want it. My 2 cents.
  • @rsmrsm2000
    Amazing! This girl researched exactly what I wanted to know. Thanks.